//***********************************************
//Project Name               :
//File Name                  :
//Author                     :ZJL
//Date of Creation           :
//Functional Description     :
//              
//Revision History           :
//Change Log                 :
//***********************************************
module ifdef(
//global input interface
    input         wire        [1-1:0]        i_Clk          ,        //27MHZ
    input         wire        [1-1:0]        i_Rst_n        ,
    input         wire        [1-1:0]        i_Pulse        
);//test
//************************parameter defination***********************


// `define DEBUG 
`ifdef DEBUG
    parameter STS_FREQ = 30 ;
`else
    parameter STS_FREQ = 30_000_000 ;
`endif
			 


reg        [16-1:0]        cnt_time1;
always @ ( posedge i_Clk ) begin
    if( ~i_Rst_n ) begin
        cnt_time1        <=        'd0;
    end
    else if( cnt_time1 ==  STS_FREQ-1)begin
        cnt_time1        <=        'd0;
    end
    else begin
        cnt_time1        <=        cnt_time1 + 'd1;
    end
end


wire        [1-1:0]         time2_add;
reg        [1-1:0]         en_cnt_time2;
reg        [16-1:0]        cnt_time2;
parameter                  CNT_TIME = 'd50;
assign time2_add = i_Pulse;
always @ ( posedge i_Clk ) begin
    if( ~i_Rst_n ) begin
        cnt_time2        <=        'd0;
    end
    else if( en_cnt_time2 )begin//只有在有效才计数
        cnt_time2        <=        cnt_time2 + 'd1;
    end
    else begin
        cnt_time2        <=        'd0;
    end
end
        
always @ ( posedge i_Clk ) begin
    if(~i_Rst_n) begin
        en_cnt_time2        <=        'd0;
    end
    else if( cnt_time2 == CNT_TIME - 1)begin//结束计数条件
        en_cnt_time2        <=        'd0;
    end
    else if( time2_add )begin        //开始计数条件
        en_cnt_time2        <=        'd1;
    end
    else begin
        en_cnt_time2        <=        en_cnt_time2;
    end
end

endmodule